It is very important to reduce parasitic capacitance of conductive lines in a wiring layer in order to achieve a higher performance of an LSI. This is particularly important to enable faster signal transmission. The ultimate technique for reducing parasitic capacitance is to form a hollow structure having a complete cavity between each adjacent two signal lines in the wiring layer.
However, in a semiconductor device including a wiring layer having such a hollow structure, nothing exists between each adjacent two signal lines in the wiring layer. Accordingly, in this case, a conductive pattern (signal line, dummy pattern or the like) in the wiring layer must serve as a main support for an interlayer insulating film serving as a floor or a ceiling of the wiring layer.
In such a case, when the conductive pattern (made of metal, for example) is thermally expanded with the increase in temperature, the interlayer insulating film is deformed. This phenomenon makes the surface of the interlayer insulating film uneven although the surface should be even.
The uneven surface of the interlayer insulating film causes the following problem. The focal point is not considerably disposed during a photo engraving process (PEP), so that a fine accurate pattern cannot be drawn on it. During a damascene process by using chemical mechanical polishing method, polishing is performed excessively or insufficiently.